| dc.rights.license | CC-BY-NC-ND | |
| dc.contributor.advisor | Wolff, Ivo de | |
| dc.contributor.author | Soest, Lars van | |
| dc.date.accessioned | 2023-08-11T00:02:32Z | |
| dc.date.available | 2023-08-11T00:02:32Z | |
| dc.date.issued | 2023 | |
| dc.identifier.uri | https://studenttheses.uu.nl/handle/20.500.12932/44636 | |
| dc.description.abstract | Hardware acceleration is the method of accelerating calculations with hardware specifically designed for the type of calculations. Accelerate and TensorFlow are libraries that make this accessible to many programmers, but these libraries differ in the level of abstraction and targeted hardware. This thesis investigates the possibility of compiling and executing Accelerate programs in TensorFlow. A compiler is introduced that converts second-order Accelerate programs to first-order TensorFlow graphs, covering 68% of the Accelerate language. | |
| dc.description.sponsorship | Utrecht University | |
| dc.language.iso | EN | |
| dc.subject | Accelerate is a language designed to compile generic parallel array instructions into hardware-specific code. This thesis proposes the addition of TensorFlow support to Accelerate’s compiler. TensorFlow is a machine learning library by Google. To compile Accelerate programs into TensorFlow, a new implementation is added to Accelerate’s compilation pipeline. This thesis investigates the possible extent of the instruction set to cover each Accelerate program and enumerates its limitations. | |
| dc.title | Compiling Second-Order Accelerate Programs to First-Order TensorFlow Graphs | |
| dc.type.content | Master Thesis | |
| dc.rights.accessrights | Open Access | |
| dc.subject.keywords | accelerate;tensorflow;hardware acceleration;compilation | |
| dc.subject.courseuu | Computing Science | |
| dc.thesis.id | 21642 | |
