Extending the BSP model to hierarchical heterogeneous architectures

Abstract

In the current field of High Performance Computing (HPC), the growing scale and complexity of problems creates a growing need for scalable parallel algorithms. To achieve scalability, we ideally want to make use of as many processors, as efficiently as possible. Many models have been (and are still) developed to describe system architectures, and to extend these models for more optimal use of newer architectures. These models form the framework for algorithm development and analysis. In this research project, an effort was made to generalise the Bulk Synchronous Parallel (BSP) model, a mathematical model for constructing and analysing parallel algorithms, to hierarchical heterogeneous architectures.